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A 142MOPS/mW integrated programmable array accelerator for smart visual processing
, D. Rossi, K.J.M. Martin, P. Coussy, L. Benini
Published in Institute of Electrical and Electronics Engineers Inc.
2017
Pages: 1 - 4
Abstract
Due to increasing demand of low power computing, and diminishing returns from technology scaling, industry and academia are turning with renewed interest toward energy-efficient programmable accelerators. This paper proposes an Integrated Programmable-Array accelerator (IPA) architecture based on an innovative execution model, targeted to accelerate both data and control-flow parts of deeply embedded vision applications typical of edge-nodes of the Internet of Things (IoT). In this paper we demonstrate the performance and energy efficiency of IPA implementing a smart visual trigger application. Experimental results show that the proposed accelerator delivers 507 MOPS and 142 MOPS/mW on the target application, surpassing a low-power processor optimized for DSP applications by 6x in performance and by 10x in energy efficiency. Moreover, it surpasses performance of state of the art CGRAs only capable of implementing data-flow portion of applications by 1.6x, demonstrating the effectiveness of the proposed architecture and computational model. © 2017 IEEE.
About the journal
JournalData powered by SciSpaceProceedings - IEEE International Symposium on Circuits and Systems
PublisherData powered by SciSpaceInstitute of Electrical and Electronics Engineers Inc.
ISSN02714310
Open AccessNo