The most computationally demanding block in the digital front end of a software defined radio (SDR) receiver is the channelizer which operates at the highest sampling rate. Reconfigurability and low complexity are the two key requirements of the SDR channelizers. An architecture for implementing low complexity and reconfigurable finite impulse response (FIR) filters for channelizers is proposed in this paper. Our method is based on the binary common subexpression elimination (BCSE) algorithm. The proposed architecture guarantees minimum number of additions at the adder level and also at the full adder (FA) level for realizing each adder needed to implement the coefficient multipliers. The proposed architecture has been synthesized on 0.18μm CMOS technology. The synthesis results show that the proposed reconfigurable FIR filter can operate at high speed consuming minimum area and power. The average reductions in area and power are found to be 49% and 46% respectively with an average increase in speed of operation of 35% compared to other reconfigurable FIR filter architectures in literature. © 2007 IEEE.