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Area Efficient VLSI Architectures for Weak Signal Detection in Additive Generalized Cauchy Noise
S.R.K. Vadali, , P. Ray, S. Chakrabarti
Published in Institute of Electrical and Electronics Engineers Inc.
2020
Volume: 67
   
Issue: 6
Pages: 1962 - 1975
Abstract
Detection of a weak signal in additive Generalized Cauchy (GC) noise is important in many applications. The locally optimum detector (LOD) for a weak signal in GC noise is nonlinear in nature. When noise variance is unknown, the maximum likelihood estimator (MLE) is nonlinear and the resultant detector is complicated. Since VLSI implementation of complex nonlinearities is a challenging task, we develop an order statistics framework for detection in GC noise. We propose linear and ratio detectors, for weak signals in GC noise with known and unknown but deterministic variance, respectively. We provide extensive simulation results to show that performance loss of proposed linear and ratio detectors, is very small compared to LOD and nonlinear detector using MLE, respectively. We propose SORT - N (for running ordering of samples) and its VLSI architecture, using which we develop two-stage VLSI architectures for proposed linear and ratio detectors. Synthesis results for arbitrary waveform case indicate, for same throughput and latency, linear detector consumes lesser area to LOD, upto a sample size of N=64. For same throughput, ratio detector renders substantial area savings (≈50%) over nonlinear detector using MLE, for any N. Finally, we propose a reconfigurable architecture for efficient realization of all the detectors. © 2004-2012 IEEE.
About the journal
JournalData powered by TypesetIEEE Transactions on Circuits and Systems I: Regular Papers
PublisherData powered by TypesetInstitute of Electrical and Electronics Engineers Inc.
ISSN15498328