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Extending trace history through tapered summaries in post-silicon validation
, P.R. Panda, D. Chauhan, S. Kumar, S.R. Sarangi
Published in Institute of Electrical and Electronics Engineers Inc.
2016
Volume: 25-28-January-2016
   
Pages: 737 - 742
Abstract
On-chip trace buffers are increasingly being used for at-speed debug during post-silicon validation. However, the activity history captured by these buffers is small due to their limited size. We propose a novel scheme that extends the captured trace history (by upto 162%) by using a portion of the trace buffer to also store summaries of trace messages. We describe an Overlapped trace buffer architecture that uses a reduced number of ports to capture tapered summaries where both detailed and summary versions of traces are stored simultaneously. We demonstrate the usefulness of the proposed methodology for debugging various classes of bugs encountered during post-silicon validation. © 2016 IEEE.