Multiple cores are preferred to meet the ever increasing computation demand of embedded systems. A multi-core system is communication intensive with on-chip wire delays and on-chip interconnects accounting for half the dynamic power dissipation. A three-dimensional (3D) stacking of dies enables low intra-chip distances for signal transmission and helps to overcome the interconnect bottleneck of multi-core systems. The 3D integration by through silicon via (TSV) can significantly improve memory-logic communication bandwidth of multi-core systems. However, the 3D multi-core system has poor heat removal capability due to position of the heat-sink. In this paper, we made a study on the thermal profile of DRAM memory layers of 3-D multi-core system. In this study, workloads are distributed to memory layers based on its thermal efficiency such that work load of heavier applications is allocated to the memory layer having highest thermal efficiency and those of lighter applications is allocated to the memory layer with lower thermal efficiency. Experimental result shows that with selective work load distribution, the average peak temperature of the 3D multi-core system is reduced than randomly allocated work load to the memory layers. A memory controller could be designed for run-time distribution of work load to the memory layers which will be addressed in the future work. © 2015 IEEE.