The most computationally demanding block of a software defined radio (SDR) receiver is the channelizer which operates at the highest sampling rate. Reconfigurability and low complexity are the two key requirements of the SDR channelizers. Two new reconfigurable architectures of low complexity finite impulse response (FIR) filters for channelizers are proposed in this paper. Our methods are based on the binary common subexpression elimination (BCSE) algorithm. The proposed architectures are capable of operating at a high speed clock frequency of 109.7 MHz based on Xilinx's Virtex II 2v2000ff896-6 FPGA for a 12-bit FIR filter coefficient. Design examples show that our method offers an average reduction of 23% in the number of addition operations compared to the conventional FIR filter implementations. © 2006 IEEE.