Indian Institute of Technology Palakkad&nbsp;(IIT Palakkad or IIT PKD) is a public autonomous&nbsp;engineering&nbsp;and&nbsp;research&nbsp;institute located in&nbsp;Palakkad,&nbsp;Kerala. It was&nbsp;one of the five new&nbsp;IITs&nbsp;proposed in the&nbsp;2014 Union budget of India. The campus was inaugurated on 3 August 2015. The institute has 94 faculty, 978 students, and 63 non-teaching staffs.

IT Palakkad currently offers four-year Bachelor of Technology (B.Tech) and two years MS programmes in 8 different engineering disciplines including&nbsp;Computer Science, Electrical, Mechanical, Civil among others.

&nbsp;

IIT Palakkad

This paper proposes a new 9-level stacked inverter for a symmetric six phase induction motor with low voltage devices using a single DC link. The six phase inverter is developed using 2 three phase 9-level stacked inverters. Each of these three phase stacked inverter is developed by stacking two 5-level inverters. The three phase 9-level inverter needs two DC sources for its operation. All the capacitors in this topology can be balanced using the switching state redundancies within a sampling interval irrespective of load power factor and modulation index. Using proper switching state redundancies, the developed six phase inverter can be operated with a single DC link. A laboratory prototype is developed and a six phase IM is run using V/f control scheme. Both steady state and transient results are presented. © 2016 IEEE.

World University root node

Department of Electrical Engineering

IEEE International Symposium on Industrial Electronics

A new nine level stacked inverter topology for a symmetric six phase induction motor with low voltage devices and using a single DC link

In this paper, a new inverter topology is proposed for generating a multilevel dodecagonal voltage space vector structure for open-end winding induction motor (IM) using a single dc source. Dodecagonal voltage space vector structure eliminates fifth- and seventh-order harmonic voltages from phase voltage output and hence eliminates the fifth- and seventh-order harmonic currents through the motor leading to removal of the dominant sixth-order torque ripple generation in the motor over the entire modulation range. Multilevel space vector structure generates output voltage with better THD and low dv/dt. In the proposed topology, two three-level inverters drive an open-end winding IM, one inverter from each side. DC-link of primary inverter is from a dc source which delivers the entire active power, whereas the secondary inverter dc-link is maintained by a capacitor, which is self balanced during the inverter operation. The PWM scheme implemented ensures low switching frequency for primary inverter. Secondary inverter operates at a small dc-link voltage. Hence, switching losses are small for both primary and secondary inverters. Experimental results show the elimination of fifth- and seventh-order harmonic voltages over the entire modulation range, validating effectiveness of the proposed multilevel inverter scheme.

IEEE Transactions on Industrial Electronics

Multilevel Dodecagonal Voltage Space Vector Structure Generation for Open-End Winding im Using a Single DC Source

A fifth and seventh order harmonic elimination scheme for IM drive with a multilevel dodecagonal voltage space vector structure using a single DC source is proposed in this work. Single DC source requirement makes four quadrant operation of the drive system simpler compared to the multilevel do-decagonal structures presented in literatures before. The space vector structure consists of six concentric dodecagons, combining the advantages of multilevel operation as well as dodecagonal structure. The topology consists of a three-level flying capacitor (FC) inverter cascaded with a capacitor fed H-bridge (CHB) inverter. The FC inverter operating at high voltage switches in a quasi-square wave mode whereas the CHB inverter operating at a lower voltage switches at high frequency to remove the harmonics generated by the FC inverter. Switching losses are low, both in the FC and CHB inverters. Experiment results for open-loop V/f operation are included in this paper showing the effectiveness of the drive scheme.

2016 18th European Conference on Power Electronics and Applications, EPE 2016 ECCE Europe

A multilevel inverter fed im drive with dodecagonal voltage space vector structure using a single DC source with linear modulation range near to base speed

This paper proposes a new forty nine level stacked inverter topology using low voltage devices for drives applications. The forty nine level inverter is developed by stacking three seventeen level inverters. The seventeen level inverter is developed by cascading a flying capacitor inverter and three H-Bridges. The inverter can operate with lower number of voltage levels if any of the H-Bridges fail. The capacitor voltage balancing in the inverter can be done irrespective of modulation index and load power factor. The topology is further modified to reduce the capacitor and switch count. Also, the inverter does not use any pulse width modulation between the different voltage levels. Therefore switching losses are reduced. In addition, since the switches need to block only lower voltages, MOSFETs can be used which will further improve the efficiency. An induction motor driven by this inverter using V/f control is simulated in MATLAB simulink and both steady state and transient results are presented. © 2016 IEEE.

IECON Proceedings (Industrial Electronics Conference)

A novel forty nine level stacked inverter topology using low voltage devices for drives

In this paper, a new three-phase hybrid seven level inverter topology with a single DC supply is proposed for the first time. The proposed inverter is realized by cascading two three level flying capacitor inverters with a half bridge module. The inverter topology is having multiple switching state redundancies for each of the pole voltage levels. By using these switching state redundancies, capacitor charging can be controlled in every PWM switching cycle. This feature is advantageous for reducing the capacitor sizing. Another advantage of the proposed inverter is that the charge balancing of each capacitor can be controlled irrespective of modulation index and load power factor. A hysteresis controller based capacitor charge control algorithm is implemented for the proposed inverter. Furthermore, the proposed topology uses lesser number of semiconductor devices, capacitors and DC power supplies compared to conventional seven level inverter topologies. The proposed topology is tested with open loop V/f control scheme in an induction motor drive. Inverter is tested for entire modulation range and experimental results for steady-state operation are presented for various fundamental frequencies. Experimental results showing the effectiveness of capacitor charge control for both steady state and transient operating conditions are presented.