Indian Institute of Technology Palakkad&nbsp;(IIT Palakkad or IIT PKD) is a public autonomous&nbsp;engineering&nbsp;and&nbsp;research&nbsp;institute located in&nbsp;Palakkad,&nbsp;Kerala. It was&nbsp;one of the five new&nbsp;IITs&nbsp;proposed in the&nbsp;2014 Union budget of India. The campus was inaugurated on 3 August 2015. The institute has 94 faculty, 978 students, and 63 non-teaching staffs.

IT Palakkad currently offers four-year Bachelor of Technology (B.Tech) and two years MS programmes in 8 different engineering disciplines including&nbsp;Computer Science, Electrical, Mechanical, Civil among others.

&nbsp;

IIT Palakkad

The complexity of linear phase Finite Impulse Response (FIR) filters used in the channelizer of a software defined radio (SDR) receiver is dominated by the complexity of coefficient multipliers. It is well known that Common Subexpression Elimination (CSE) methods based on Canonical Signed Digit (CSD) coefficients produce low complexity FIR filter coefficient multipliers. A new CSE algorithm based on the binary representation of filter coefficients is presented in the paper. Design examples of channel filters employed in the Digital Advanced Mobile Phone Systems (D-AMPS) and Personal Digital Cellular (PDC) receivers show that the proposed method offers an average adder reduction of 23% over the conventional CSD-based CSE method. © 2006 IEEE.

Department of Electrical Engineering

Proceedings - IEEE International Symposium on Circuits and Systems

A new common subexpression elimination algorithm for implementing low complexity FIR filters in software defined radio receivers

The most computationally demanding block of a software defined radio (SDR) receiver is the channelizer which operates at the highest sampling rate. Reconfigurability and low complexity are the two key requirements of the SDR channelizers. Two new reconfigurable architectures of low complexity finite impulse response (FIR) filters for channelizers are proposed in this paper. Our methods are based on the binary common subexpression elimination (BCSE) algorithm. The proposed architectures are capable of operating at a high speed clock frequency of 109.7 MHz based on Xilinx's Virtex II 2v2000ff896-6 FPGA for a 12-bit FIR filter coefficient. Design examples show that our method offers an average reduction of 23% in the number of addition operations compared to the conventional FIR filter implementations. © 2006 IEEE.

IEEE International Symposium on Personal, Indoor and Mobile Radio Communications, PIMRC

Reconfigurable low complexity FIR filters for software radio receivers

Two dimensional (2-D) image convolution is a typical algorithm executed by window-based spatial domain filters, which are in turn used in many applications including intrusion detection. Systolic arrays have been widely used in them by exploiting the hardware parallelism on FPGAs to increase the throughput of the system. These implementations differ mostly in the processing element (PE) architecture employed. We propose a new scheme for the PE in the systolic array architecture which uses a novel area-time efficient lookup table (LUT) based method and reduces the LUT resource usage by almost 50% when compared to the conventional constant coefficient LUT based method. © 2006 IEEE.