Indian Institute of Technology Palakkad&nbsp;(IIT Palakkad or IIT PKD) is a public autonomous&nbsp;engineering&nbsp;and&nbsp;research&nbsp;institute located in&nbsp;Palakkad,&nbsp;Kerala. It was&nbsp;one of the five new&nbsp;IITs&nbsp;proposed in the&nbsp;2014 Union budget of India. The campus was inaugurated on 3 August 2015. The institute has 94 faculty, 978 students, and 63 non-teaching staffs.

IT Palakkad currently offers four-year Bachelor of Technology (B.Tech) and two years MS programmes in 8 different engineering disciplines including&nbsp;Computer Science, Electrical, Mechanical, Civil among others.

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IIT Palakkad

A radio frequency micro-electro-mechanical system (RF-MEMS) 5 bit phase shifter based on a distributed MEMS transmission line concept with excellent phase accuracy and good repeatability is presented in this paper. The phase shifter is built with three fixed-fixed beams; one is switchable with electrostatic actuation and the other two are fixed for a metal-air-metal (MAM) capacitor. The design is based on a coplanar waveguide (CPW) configuration using alumina substrate. Gold-based surface micromachining is used to develop the individual primary phase bits (11.25°/22.5°/45°/90°/180°), which are fundamental building blocks of the complete 5 bit phase shifter. All of the primary phase bits are cascaded together to build the complete phase shifter. Detailed design methodology and performance analysis of the unit cell phase shifter has been carried out with structural and parametric optimization using an in-line bridge and MAM capacitors. The mechanical, electrical, transient, intermodulation distortion (IMD), temperature distribution, power handling and loss performances of the MEMS bridge have been experimentally obtained and validated using simulations up to reasonable extent. A single unit cell is able to provide 31 dB return loss, maximum insertion loss of 0.085 dB and a differential phase shift of 5.95° (at 10 GHz) over the band of interest. Furthermore, all primary phase bits are individually tested to ensure overall optimum phase shifter performance. The complete 5 bit phase shifter demonstrates an average insertion loss of 4.72 dB with return loss of better than 12 dB within 8-12 GHz using periodic placement of 62 unit cells and a maximum phase error of ±3.2° has been obtained at 10 GHz. Finally, the x-band 5 bit phase shifter is compared with the present state-of-the-art. The performance of the 5 bit phase shifter when mounted inside a test jig has been experimentally investigated and the results are presented. The total area of the phase shifter is 19.4 mm2. To the best of our knowledge, this is the first reported digital distributed MEMS transmission line type RF-MEMS phase shifter that has undergone different reliability stages. © 2014 IOP Publishing Ltd.

Department of Electrical Engineering

World University root node

Journal of Micromechanics and Microengineering

Design, development and characterization of an x-band 5 bit DMTL phase shifter using an inline MEMS bridge and MAM capacitors

Insulated gate bipolar transistors (IGBTs) are used in high-power voltage-source converters rated up to hundreds of kilowatts or even a few megawatts. Knowledge of device switching characteristics is required for reliable design and operation of the converters. Switching characteristics are studied widely at high current levels, and corresponding data are available in datasheets. But the devices in a converter also switch low currents close to the zero crossings of the line currents. Further, the switching behaviour under these conditions could significantly influence the output waveform quality including zero crossover distortion. Hence, the switching characteristics of high-current IGBTs (300-A and 75-A IGBT modules) at low load current magnitudes are investigated experimentally in this paper. The collector current, gate-emitter voltage and collector-emitter voltage are measured at various low values of current (less than 10% of the device rated current). A specially designed in-house constructed coaxial current transformer (CCT) is used for device current measurement without increasing the loop inductance in the power circuit. Experimental results show that the device voltage rise time increases significantly during turn-off transitions at low currents. © 2014 IEEE.

Proceedings of the 2014 IEEE 2nd International Conference on Electrical Energy Systems, ICEES 2014

Experimental investigation on switching characteristics of high-current insulated gate bipolar transistors at low currents

In this paper, we consider a fault tolerant control system (FTCS) with state- dependent failures and provide a tractable mathematical model to handle the state-dependent failures. By assuming abrupt changes in system parameters, we use a jump process modelling of failure process and the fault detection and isolation (FDI) process. In particular, we assume that the failure rates of the failure process vary according to which set the state of the system belongs to. © Published under licence by IOP Publishing Ltd.

Journal of Physics: Conference Series

A novel mathematical setup for fault tolerant control systems with state-dependent failure process

We report the room temperature fabrication of Ta/TiO2/Ta metal–insulator-metal (MIM) capacitors (mainly, for DRAM applications). The fabricated devices show high capacitance density ($\sim$15 fF/$\mu$m2) and...

Physics of Semiconductor Devices

Room Temperature-Processed TiO2 MIM Capacitors for DRAM Applications

A novel active soft switched phase-shifted full-bridge (PSFB) dc-dc converter is presented in this paper. An auxiliary circuit is added to the pulse width modulation counterpart to achieve the soft switching. The proposed circuit achieves soft switching for both main and auxiliary switches, without increasing the main device current/voltage rating. The auxiliary circuit is gated appropriately in order to achieve zero voltage switching for lagging leg. Tapping in the primary winding of power transformer is added for the purpose of commutation. The proposed circuit is capable of operating at elevated switching frequencies of several hundreds of kilohertz in a range of line and load variations. Steady-state analysis and evaluation of losses for the proposed circuit is presented. Analytical models valid for steady state and dynamic performance are proposed. A 350-W, 100-kHz active soft switched PSFB dc-dc converter prototype is implemented. The proposed analytical models are validated experimentally on 350-W prototype. Experimental results verifying steady state and dynamic models are presented. © 1986-2012 IEEE.

IEEE Transactions on Power Electronics

An active soft switched phase-shifted full-bridge DC-DC converter: Analysis, modeling, design, and implementation

In this paper, we present an automatic method for determining time-location of systolic peak in arterial blood pressure (ABP) signals. The method consists of four major steps: Gaussian derivative filtering, nonlinear peak amplification, Gaussian derivative based peak finding scheme, and peak position adjustment procedure. The method is tested and validated using the standard MIT-BIR Polysomnographic database containing a wide range of ABP signals, artifacts and high-frequency noises. Our results demonstrate that the proposed method can achieve better peak detection performance while maintaining very small detection error rates for both clean and noisy ABP signals. The method achieves an average sensitivity of 99.89% and positive predictivity of 99.59% on test ABP datasets consisting of 67,125 beats. Unlike other existing methods, our method is quite straightforward and simple in the sense that it does not use search-back algorithms with secondary thresholds. © 2014 IEEE.

Proceedings of the 2014 IEEE Students' Technology Symposium

An automated method for detecting systolic peaks from arterial blood pressure signals

This paper deals with an optimization schemes and CORDIC circuit for fixed and known rotations different level of accuracy. For reducing area and time complexity. This paper proposed hard wired, pre-shifting technique for barrel-shifter of proposed circuit. Here two proposed CORDIC cells are used to the fixed angle rotations. This cells going to implement the micro rotations and scaling interleaved, it's implemented the two stages. The cascade proposed the bi-rotation CORDIC for higher throughput and reduced latency implementation. This method proposed optimized set of micro rotations for fixed and known angles. Shift and add circuits are used to implement the scaling factor. Fixed means square error used for analysis and reduced the error in this method. Synthesized the proposed CORDIC cells by Synopsys Design Compiler using TSMC 90-NM library and shown that the proposed designs offer higher throughput, less latency and less area-delay product than the reference CORDIC design for fixed and known angles of rotation. We find similar results of synthesis of different Xilinx field-programmable gate-array platforms. © 2014 IEEE.

International Conference on Communication and Signal Processing, ICCSP 2014 - Proceedings

Area and time efficient hardwired pre -shifted bi-rotation CORDIC design

Department of Mathematics

Mississippi State University Scholars Junction

Classes of Singular Nonlinear Eigenvalue Problems with Semipositone Structure

We give an N · log N · 2O(log*N) time algorithm to multiply two N-bit integers that uses modular arithmetic for intermediate computations instead of arithmetic over complex numbers as in Fürer's algorithm, which also has the same and so far the best known complexity. The previous best algorithm using modular arithmetic (by Schönhage and Strassen) has complexity O(N · log N · log log N). The advantage of using modular arithmetic as opposed to complex number arithmetic is that we can completely evade the task of bounding the truncation error due to finite approximations of complex numbers, which makes the analysis relatively simple. Our algorithm is based upon Fürer's algorithm, but uses fast Fourier transform over multivariate polynomials along with an estimate of the least prime in an arithmetic progression to achieve this improvement in the modular setting. It can also be viewed as a p-adic version of Fürer's algorithm. © 2013 Society for Industrial and Applied Mathematics.